1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device which generally necessitates the use of two or more polycrystalline silicon layers and which requires there to be a large capacitive coupling between the polycrystalline silicon layers and, more particularly, to a method of manufacturing a semiconductor memory device such as an EPROM, an EEPROM, and a DRAM.
2. Description of the Related Art
Conventionally, EPROMs (or EEPROMs) are manufactured by forming a thin insulating film between two polycrystalline silicon layers; that is, after a first polycrystalline silicon layer is formed, an impurity such as phosphorus is doped therein. Subsequently, a desired region of the first polycrystalline silicon layer is selectively removed by way of photolithography and RIE processes, and the surface of the first polycrystalline silicon layer is thermally oxidized to form a thin oxide film. Thereafter, a second polycrystalline silicon layer is formed and patterned.
FIG. 1 shows a sectional structure of an EPROM (or an EEPROM) formed by use of the above conventional manufacturing method. In FIG. 1, reference numeral 11 denotes a silicon substrate; 12, an element isolation region; 13, a gate insulating film; 14, a first polycrystalline silicon layer; 15, a thin insulating film (oxide film); and 16, a second polycrystalline silicon layer. Although not shown, source and drain regions are formed in front of and behind the structure.
Recently, scaling down is required for semiconductor device. In order to satisfy this requirement dimensions, if thickness of insulating film 15 is designed to be thin, and film 15 is formed at a low temperature so as to prevent expansion of a diffusion layer formed in substrate 11, the following problems are posed. That is, as shown in FIG. 2, region A encircled within a broken line in FIG. 1 is illustrated in an enlarged scale, only insulating films 15a and 15b which are thinner than a flat portion are formed at corner portions of layer 14. For this reason, an effective withstand voltage of the element is reduced. Moreover, when thinner film 15 is formed at a low temperature, edge portions 14a and 14b of layer 14 are not rounded, with the result that field enhancement tends to occur thereat. Field enhancement also causes a reduction in the element electric field strength. In addition, side wall portion 14c of layer 14 is damaged or contaminated by the RIE process performed when layer 14 is patterned. As a result, vertical portion 15c of film 15 formed on side wall portion 14c, generally has tends to have many defects. These defects reduce the manufacturing yield of the device. Furthermore, since the conventional manufacturing method requires that a photoresist be used in the patterning of layer 14, prior to the formation of insulating film 15, this results in the surface of layer 14 being contaminated. As a result of this contamination, whole number of defects generated in film 15 is increased or movable ions are trapped therein, thereby destabilizing the element characteristics and degrading the reliability of the element.